Contest in China proposes to make AMD’s Zen architecture compatible with RISC-V

The discovery of severe vulnerability in CPUS architecture AMD Zen 1, 2, 3 and 4 was seen as an opportunity by Jiachen Project in China. The failure allows you to rewrite part of the processor microcode based on past generations of Zen technology, and the Chinese project wants to see programmers taking advantage of this to make these CPUs natively compatible with RISC-V.

This is why Jiachen Project started a new contest, offering a cash prize for those who make, for example, an AMD EPYC running Risc-V natively-or at least with optimized performance. The work should be proven through synthetic benchmark tests, such as Coremark and Dhrystone, focused on RISC-V.

Competition participants should deliver their work by June 6, and can only offer only binaries, provided that the source code is delivered shortly thereafter. The prize is 20,000 yuans, which gives a little over $ 16,000 in the current price.

Risc-V has been popular, but its adoption is not yet compared to mainstream technologies as x86-64 or arm. Thus, there are few hardware options dedicated to the platform, even more high performance. Jiachen Project then seems to want to take a shortcut and get Zen CPUS ready for the format in a very short time.

Making Amd Zen Risc-V Changing Microcode can be impossible

Project critics claim that the contest can be a waste of time. For starters, it is possible that it is not possible to access the entire processor microcode through the vulnerability exploited by zentool.

Also, even if it was possible to change the todinho microcode, this may not be enough to make a Zen CPU run Risc-V natively, or something close to that. The feature was created more to fix any processor bugs or failures, not to completely reprogram its operation.

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Finally, programmers also question the value of the prize. It is a complex work that demands time, and a programmer can earn better than that in other jobs.

Source: Tom’s Hardware