TSMC plans 1000W overprcesses with performance 40 times larger than current models

TSMC is preparing a new revolution in the chip market for AI date centers and applications. The company announced, during its North America Technology Symposiumwhich is developing a new generation of multi-choplet packages that can reach incredible 1000W of consumptionhousing interposers with Area up to 9.5 times larger that the current photomascara limits.

Com Substrates of up to 120 × 150 mm (18,000 mm²) – Almost the size of a CD box – technology can support up to 40 times more performance than conventional chips, positioning the largest semiconductor founding company in the world as a reference in advanced packaging for high performance computing.

Climbing the limits of packaging

Currently, technology CoWoS TSMC already allows for interposers from up to 2831 mm²used by giants as AMD (Instinct MI300X) e NVIDIA (B200)which combine multiple logical chipples with HBM3 memory piles.

However, growing demand for more computational power has made the company a new plan: the 3DFabric Roadmapwhich aims to significantly broaden the dimensions of the interposers.

The next step will be the arrival of technology New generation cowos-lwith interposers from up to 4719 mm² and support for 12 Batteries of HBMmounted on substrates of 100×100 mm (10.000 mm²). This phase should already offer 3.5 times more performance that the current designs.

For clients who require extreme performance and are willing to pay for it, we offer technologies such as SOWX, with WAFER integration

Next Border: Stacking chipples and wafer-level integration

The next step, focused on even more demanding applications, will include 3D Assemblies with up to four stacked systems (SOIC) – Combining us as n2/a16 on chips n3 -, 12 Batteries of HBM4 e dedicated i/o diesall this mounted on an interposition of 7885 mm²the largest planned by the company.

For niche clients, like Brains e TeslaTSMC also bets on the approach System-on-Wafer (SoW-X)where the whole system is built on a complete wafer, eliminating the physical boundaries of conventional packages.

Energy Delivery: The Next Challenge of Kilowatt Chips

Feeding these computational monsters with sufficient energy is one of the biggest challenges in the industry. TSMC intends to solve this integrating Energy Management Circuits (PMICS) based on its technology N16 FinFET directly in the interposers with RDL (Redistribution Layers).

With the help of TSVS (vertical roads) e Inductors in Wafer himselfit will be possible to deliver current efficiently and reduce parasite resistance losses.

In addition, the packages will have Embedded Capacitors (EDTCS) with density of up to 2500 nF/mm²responsible for softening voltage variations and maintaining system stability even under intense and dynamic workloads.

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Impact on design and refrigeration

These superchips require much more than just packaging and energy advances. The size of the proposed substrates exceeds the limits of the current standard OAM 2.0which measures 102 × 165 mm. This indicates that new formats of modules and motherboards will need to be developed.

In terms of refrigeration, traditional solutions will not be sufficient. Hardware manufacturers are already testing direct liquid cooling e total immersioncrucial technologies to deal with heat levels generated by multiple kilowatts chips. Own NVIDIA already adopts these techniques in their designs NVL72 com GPUs GB200/300.

Source: TSMC