TSMC optimizes 2nm chips by 6% and passes savings on to customers

On his profile on X, formerly Twitter, one of the TSMC employees, known as Dr. Kim, mentioned that his team managed to increase the yields of 2 nm test chips by 6%. As a result, they created “billions in savings” for the company’s customers.

Dr. Kim did not reveal whether the foundry improved the yields of SRAM test chips or logic test chips. Considering that TSMC will begin offering its test wafer services for 2nm technology in January, the company is unlikely to improve yields for current chip prototypes that will be replaced by 2nm models.

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TSMC is currently set to begin mass production of semiconductors using its N2 (class 2nm) manufacturing process in the second half of next year. For now, the company is striving to improve technology in terms of reducing variability and defect density, thereby improving yields.

Improving the yields of SRAM and logic test chips is very important, as this can eventually translate into significant savings for customers, who pay for wafers and therefore benefit from higher yields.

Expected performance

Chips made using N2 manufacturing technology are expected to consume 25% to 30% less power at the same transistor count and frequency than chips made using the N3E manufacturing process.

They are also expected to offer a 10% to 15% performance increase with the same transistor count and power, and offer a 15% increase in transistor density while maintaining equivalent speed and power compared to semiconductors made by the N3E process.

As TSMC is expected to begin mass production of chips with its N2 manufacturing process from the second half of 2025, perhaps not until the end of 2025, it is possible that the world’s largest contract chipmaker will be able to improve yields further.

Process N2

N2 will be TSMC’s first manufacturing process to use gate-all-around (GAA) nanosheet transistors. The process promises substantial energy reduction, increased performance and transistor density.

In particular, TSMC’s GAA nanosheet transistors are not just smaller than 3nm FinFET transistors. They also enable smaller high-density SRAM bit cells, offering better electrostatic control and reducing leakage without compromising performance.

The resulting design improves threshold voltage tuning, ensuring reliable operation and enabling further miniaturization of logic transistors and SRAM cells.

The future of TMSC

Taiwan Semiconductor Manufacturing Company is one of Taiwan’s largest companies, one of the most valuable semiconductor companies and the largest independent semiconductor factory in the world. However, currently, it should not produce 2nm chips outside its country of origin due to local legislation.

There is already a unit installed in Arizona, USA, which managed to reach Taiwanese production in tests, but only between 2029 and 2030 is it expected to produce 2nm chips on American soil.

Source: Dr Kim and Tom’s Hardware.