TSMC 2nm process has density of defects (D0) lower than predecessors

TSMC released in a recent US symposium on density of defects (D0) for its latest process, N2, which results in 2NM lithography. The company has shown that moving to a new manufacturing technology has not caused it problems, reaching less than predecessor processes at the same time as production.

The chart below compares the density of defects in the company’s latest processes, from N7 and N6 to N2. The axis of time compares generations in relation to its height in production. N2 is two quarters of starting to be produced in mass, so that’s where your line, blue, to.

Combining with other TSMC processes at the same time, two quarters before mass production, we can see that N2 has the lowest density of density among them all.

Density decreases as production advances. It is possible to see that N7 and N6 never reached the least reached by the latest. N5 and N4 were the ones that had the defects decreasing faster, but N3 and N3P reached the same density eventually.

TSMC is not afraid of Gate-All-Arynd

What draws the most attention in the chart is that the N2 process will mark the first time TSMC uses Gate-All-Around (GAA) in the manufacture of chips. Previous generations employed the much more established finfet.

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The introduction of a new technology often causes problems, but in this case it seems that at least in the density part of GAA technology did not bring problems to the Taiwanese giant of semiconductors.

Perhaps this is also why the company already wanted to anticipate and reveal its future 1.4nm lithography as early as this week, promising to reach mass production in 2028. Meanwhile, process N2 already has confirmed clients for their first chips.

Via: Tom’s Hardware