South Korean engineers envision 0.2nm chips and monolithic 3D structures within 15 years

The Institute of Semiconductor Engineers (ISE) presented its Semiconductor Technology Roadmap 2026, which makes predictions for the development of silicon over the next 15 years. Among the predictions, These include the increase in NAND flash memory layers from 321 to 2,000.

Semiconductors for artificial intelligence capable of carrying out tens of trillions of operations per second would also be planned.

According to the ETNews report, the objective of the roadmap is “to contribute to strengthening the competitiveness of the semiconductor industry and technology in the long term, activating academic research and establishing human resources development strategies”.

It encompasses nine core technologies: semiconductor devices and processes; semiconductors for artificial intelligence; semiconductors for optical connection; semiconductor sensors for wireless connection; semiconductors for wired connection; PIM (Infrastructure Processing); encapsulation; and quantum computing.

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The cheapest lithography technology currently belongs to Samsung’s 2nm Gate-All-Around (GAA) technology. However, the Korean giant has already planned improved variants of this manufacturing process.

For example, the company has completed the basic design of its second-generation 2nm GAA node and plans to implement SF2P+, the third-generation 2nm GAA technology, within two years.

It is estimated that, by 2040, The 0.2nm process will employ a state-of-the-art transistor structure, the CFET (Complementary Field Effect Transistor), and a 3D monolithic design.

Currently, Samsung is South Korea’s leader in manufacturing next-generation semiconductors. And the company has also reportedly formed a team to begin research into developing 1nm chips, with the aim of starting mass production in 2029.

These improvements will not only apply to SoCs for mobile devices, but also to DRAM, whose memory circuit will be reduced from 11 nm to 6 nm. High bandwidth memory (HBM) is also expected to benefit and advance from 12 layers and 2 TB/s of bandwidth to 30 layers and 128 TB/s of bandwidth.

As for NAND, where SK hynix developed 321-layer QLC technology, advances in semiconductors will enable the creation of 2,000-layer QLC NAND.

Finally, what we currently have are AI processors that can reach 10 TOPS (trillions of operations per second). However, the report’s predictions are that, within a decade and a half, it will be possible for chips to generate 1,000 TOPS per second for learning and 100 TOPS for inference.

Source: ETNews, translated by WCCFTECH.