HBM4: Jedec officializes the ultra -rare memory pattern for the age of artificial intelligence

A JEDEC Solid State Technology Association Officially announced the new specification for memories HBM4 (High Bandwidth Memory 4), under the denomination JESD238.

The pattern brings significant advances in bandwidth, density and energy efficiency, aiming to supply the growing demand for applications in artificial intelligence, high performance computing (HPC) and state -of -the -art data centers.

Advances in Performance and Architecture

HBM4’s new architecture maintains the dies dies vertical stacking characteristic, but with structural changes that double the canal capacity by stack: now they are 32 independent channelsagainst the 16 of the HBM3, each divided into two pseudo-camper.

With this configuration, it is possibleR transfer speeds up to 8 GB/s in a 2048 -bit interfacetotaling an impressive bandwidth of up to 2 tb/s per pile.

In addition, HBM4 has separate data and command buses, allowing parallel operations with less latency – a significant gain for simultaneous workloads, common in AI and HPC environments.

The evolution of the technology standard for HBM memories

Notes:

• ¹ HBM3 can use multiple parallel interfaces (Dual 1024-bit) to reach 2048 bits.
• HBM4 is the first generation with Data bus separate from commandsimproving competition and parallelism.
• HBM4 introduces significant physical improvements to support higher signal stability speeds.

In terms of efficiency, the JESD270-4 standard introduces power flexibility supported by various voltage combinations: VDDQ can operate at 0.7V, 0.75V, 0.8V or 0.9V, while VDC operates at 1.0V or 1.05V.

What changes? This allows manufacturers optimize energy consumption according to system needscontributing to a more sustainable and adaptable operation.

Compatibility and ease of adoption

Another important highlight of HBM4 is yours retrocompatibility with HBM3 controllers, allowing existing controllers to operate with both standards. The technique reduces adoption barriers and promotes greater flexibility in the development of hybrid systems.

The HBM4 specification facilitates the adoption of faster and denser memory solutions, without requiring drastic changes in the existing control infrastructure

Improved reliability and greater density

The standard also incorporates the Directed Refresh Management (DRFM) feature, which improves the mitigation of wear effects such as Row Hammer, as well as providing improvements in reliability, availability and maintenance capacity (RAS). ]

The HBM4 batteries now support settings from 4 to 16 dies, with densities of up to 32GB by DIE, which enables memory cubes up to 64 GB of capacity.

Renewed physical interface and integrated tests

With a new physical interface and improvements in signal integrity, HBM4 is prepared to sustain higher transfer rates with stability.

Also included were mechanisms of internal testing, such as support for the IEEE 1500 standard and loopback modes, as well as automatic calibration and real -time failure repair mechanisms.

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Industrial collaboration and availability

The creation of the specification had the collaboration of large memory manufacturers, including Samsung, SK Hynix and micron. The first samples and commercial products compatible with HBM4 should begin to be presented to the market in 2025, aligning with the growing demand of AI and Hyperscalers chip developers.

Source: JEDEC