Marvell announced this week a new technology for customized HBM memories (CHBM) that promises to optimize the performance and efficiency of components, while reducing the space they occupy on the die. The new memories will be compatible with Marvell’s own customized XPUs at first.
As CHBM are not yet standardized by JEDEC, the manufacturer announced a partnership with some of the largest memory companies in the world to guarantee the implementation of the components. Among them, Micron, Samsung and SK Hynix were highlighted.
Marvell’s new memories were presented during the company’s keynote at Analyst Day 2024. Photographs of some of the slides shown reveal some details of the company’s promises for its new products. Among them, we have:
- Increased die-to-die I/O performance
- Up to 70% lower interface power consumption
- Up to 25% larger area for XPU silicon
- Space for up to 33% more HBM stacks
Another interesting point about CHBM memories is that, as they are customized, they can also be optimized for specific applications, upon customer request. The folks at Tom’s Hardware claim that Marvell promises bandwidth of up to 20Tbps/mm (625GBps/mm) in components. Over time, the manufacturer wants to deliver components with up to 50Tbps/mm (6.25TBps/mm), without buffering.
Marvell continues to focus on AI that boosted its shares
Marvell recently managed to surpass Intel in market value, after releasing a financial report that exceeded market analysts’ expectations. To a large extent, such positive numbers for the company were made possible by the AI hype, which boosted sales of its products.
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Therefore, it is clear that the company’s focus on disseminating CHBM was also on improvements in technology. “Improving XPUs by refining HBM for specific performance, power and total cost of ownership is the latest step in a new paradigm in the way AI accelerators are created and distributed,” said Will Chu, a Marvell executive. He adds:
“We are grateful to work with leading memory designers to accelerate this revolution and help data center operators continue to scale their XPUs and infrastructure for the AI era.” We still don’t have all the details about CHBM, so we don’t know where this version of memories fits in relation to the HBM3E and HBM4 standards, for example.
Via: Tom’s Hardware
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Source: https://www.adrenaline.com.br/hardware/marvell-revela-hbm-customizado-prometendo-mais-performance-em-menos-espaco/
