2D transistors closer to reality: Intel details production compatible with 300 mm wafers

2D transistors based on 2D materials have been demonstrated in academic settings and research laboratories for over a decade. However, none of these demonstrations were compatible with large-scale semiconductor manufacturing.

The problem is that they rely on small wafers, custom search tools, and fragile process steps.

This week, Intel Foundry and imec demonstrated an integration of critical process modules for 300mm wafer-ready 2D field effect transistors (2DFETs). Everything indicates that 2D materials and 2DFETs are getting closer to reality.

Related News:

Limits of Current Technology

Technologies such as Intel’s 18A, Samsung’s SF3E and TSMC’s N2 use devices with a gate-all-around (GAA) structure. And all major chipmakers are also developing complementary FETs (CFETs) to stack transistors vertically and extend density gains beyond what is possible with GAA.

CFETs are considered the next step beyond gate-all-around transistors and are expected to emerge in the next decade.

However, Intel and other chipmakers argue that continued miniaturization will eventually push silicon channels to their physical limits. At this point, electrostatic control and carrier mobility degrade due to the extremely small dimensions.

The industry is increasingly evaluating 2D materials to solve this problem. After all, 2D materials can form channels just a few atoms thick while maintaining strong current control.

Blue results

Intel and imec presented a paper at IDM that details their work with the family of transition metal dichalcogenides (TMDs). In the demonstrated structures, WS₂ and MoS₂ were used for n-type transistors, while WSe₂ served as p-type channel material.

Although these compounds have been studied for years, the main challenge has been integrating them into a 300mm wafer fabrication flow without damaging the fragile channels. Another problem is relying on processing steps that cannot be performed reliably in a large-scale production environment.

The main innovation presented by Intel and imec is a contact and port integration scheme compatible with large-scale manufacturing. Intel has grown high-quality 2D layers and coated them with a multilayer stack of AlOₓ, HfO₂ and SiO₂.

Next, carefully controlled selective oxide etching allowed the formation of superior Damascene-style contacts. This step preserves the integrity of the underlying 2D channels, which are highly sensitive to contamination and physical damage..

This Damascene-style top-contact approach also solves one of the biggest challenges in developing 2DFETs: form scalable, low-resistance contacts using processes compatible with production tools.

In addition to contacts, Intel and imec also demonstrated manufacturable gate stack modules, a major hurdle that has historically impeded the industrial integration of 2D devices.

Technology for 2040

The importance of this joint work between Intel and imec does not lie in immediate commercialization. T2D ransistors based on 2D materials belong to a distant future, perhaps in the second half of the 2030s or even the 2040s.

The value of the work is more related to reducing risks in the development and eventual production of chips that will use 2D materials.

When validating contact and port modules in a production environment, Intel Foundry enables customers and internal design teams to evaluate 2D pipelines using realistic and scalable process assumptions. This approach aims to accelerate device benchmarking, compact modeling, and early design exploration.